The present invention relates to serializer deserializer functions used in data communications and more particularly to a serializer deserializer function fully integratable on a single module substrate.
Serializer deserializer modules use a deserializer voltage controlled oscillator, which is part of a phase locked loop, and which operates at a frequency which is the bit rate of the received serial bits to retime the serial bit stream. The serializer is used to generate the serial bit stream. The serializer VCO typically has the same center frequency as the deserializer VCO since data is sent at the same rate at which data is received in present data links. With the data being sent and received at the same rates buffering requirements are reduced. The input stage of latching by the deserializer is done with a full speed clock so all bits are clocked into the input latch transition at the same phase, relative to the data bit edges.
Due to "near-frequency" noise problems it is very difficult to fully integrate a complete serializer deserializer function on a single module substrate. One of the problems is the voltage controlled oscillators (VCOs), which are part of phase locked loops, running at the same frequency and in close proximity to one another tend to interact. This interaction can be in the form of power supply noise, substrate noise, and radiated RF noise.
It is an object of the present invention to provide a serializer deserializer circuit implementable on the same module substrate with substantially reduced near frequency noise generation between the VCO's of the serializer and deserializer.
It is a further object of the present invention to provide a serializer deserializer with reduced near frequency noise problems that is easily implementable using existing design procedures.
It is another object of the present invention to provide a serializer deserializer circuit implementable on a single module substrate which provides a deserializer VCO which has less output jitter.
It is still another object of the present invention to provide a serializer deserializer circuit implementable on a single module substrate which is extendable to multi-gigabit rates.